The present invention generally relates to automated manufacture systems and methods and, more particularly, relates to automated and robotic semiconductor equipment systems and methods, particularly for testing and quality control, and improvements thereto, including reduction of index timing delays and the like.
Automated manufacturing equipment has streamlined the manufacturing process in many industries. Moreover, such automation has increased reliability and results. A downside of automation has been timing delays in equipment operations. Particularly, where expensive manufacturing equipment is involved, delays in operations of the equipment, such as during mechanical movements in transferring devices under test, limit returns on the costs of such equipment because of idle or non-testing use periods during mechanical manipulations, resets, and the like. An impetus in manufacturing technology and operations has, therefore, been to limit times in which costly test equipment is idle and not performing the applicable test function, for example, when robotically substituting next test pieces.
In semiconductor manufacture, semiconductor device test equipment is a costly capital requirement. Conventionally, such test equipment has included a robotic manipulator for handling the devices being tested. This robotic manipulator system is commonly referred to as a “handler” and is typically configured with one or more robotic arms referred to as “manipulators.” The manipulator mechanically picks up a device for testing, inserts the device into an interface test board socket and issues a start-of-test signal to the tester. The tester then conducts a test on the device and returns a test result and an end-of-test signal to the handler which causes the handler to disposition the device to a post-test tray or receptacle for holding tested devices. This process is repeated as long as the handler senses that there are additional devices available for test. This system as a whole is sometimes referred to as a “test cell.”
During the time required for the handler to disposition a device(s) just tested and replace it with the next device(s) to be tested, the tester remains substantially idle. This idle time, sometimes referred to as the “index time” for the particular tester and system, involves mechanical manipulations of the devices awaiting test and having been tested. These mechanical manipulations are limited in speed of operations by various factors, including, for example, physical and speed constraints to ensure that devices to be tested are not damaged, contaminated, dropped, and the like.
The time required to test a device is sometimes referred to as “test time” for a particular device, test, tester, and system. When the system is operational in a manufacturing capacity, it is either indexing during the index time or otherwise testing during the test time.
Previously, test equipment manufacturers have focused efforts to reduce index time on design of manipulation equipment to increase speed of mechanical operations. Although speeds of mechanical operations in handling the test devices have increased significantly over time, there nonetheless remains significant mechanical index time required to manipulate test devices between tests, by the robotic handlers. Moreover, with increased speeds of mechanical manipulation equipment operations, costs increase for the equipment, including calibration, replacement frequency, maintenance, parts, and others. Given the constraints and precautions that must be addressed in speeding mechanical manipulations of many types of test devices and handlers, further speeding of mechanical operations is subject to economic and physical barriers.
In any event, reducing index time can provide greater returns on investments in test equipment, particularly where the test equipment is costly. It would, therefore, be a significant improvement in the art and technology to further reduce index time involved in test operations in manufacturing environments. Particularly in semiconductor manufacture, economic and other gains and advantages are possible if index times are reduced in the testing of semiconductor devices. It would also be an improvement to provide new and improved systems and methods for achieving reduced index times, without requiring substantial changes or new developments in existing mechanical operations of device handlers and similar robotic or automated components for the testing.
For purposes of background understanding, conventional testing systems and operations are now described:
Referring to FIG. 1, a conventional system 100 for testing a device 102 (also referred to herein as “device under test” and/or “DUT”) includes a tester 104, an interface board 106 connected to the tester 104 that makes available the tester 104 resources (e.g., testing protocols, signals, and procedures run by the tester) to the device 102 under test, and a robotic handler 108. It is to be understood that the device 102 can be a single device or multiple devices simultaneously connected to the tester and tester resources for concurrent testing operations, but that the singular term “device” is used herein to refer to devices that are so simultaneously connected and concurrently tested. The robotic handler 108 is communicatively connected to the tester 104. The interface board 106 is communicatively connected to the tester 104. The interface board 106 includes a test socket 110 for receiving and maintaining the device 102 during testing.
The test socket 110 provides a physical mechanism that assists a manipulator arm 109 of the handler 108 in the alignment of the device 102 under test, so that electrical contact between the device 102 under test and the tester 104 is adequately maintained while the device 102 is undergoing electrical test. Typically the precision of the manipulator arm 109 is too course to (itself alone) provide and maintain proper electrical contact between the device 102 under test and the tester 104 and relevant tester resources, and it is the test socket 110 which provides the mechanics of fine alignment required to maintain proper electrical contact during test. It is also to be understood that the test socket 110 can be a single socket for device(s) or multiple sockets for device(s) simultaneously manipulated, retained, and transferred or positioned for testing by the manipulator arm 109 of the robotic handler 108 in each successive manipulation of next device(s) to be tested.
For example, in certain configurations, a chuck (i.e., device retention mechanism) of the manipulator arm 109 can pick up more than one device (e.g., two devices in the same pass of the manipulator arm 109) for testing, and then position each of the devices at respective sockets available for the devices. The respective sockets in such configuration are physically connected in parallel to the tester 104 (and its test resource), but the tester 104 (and test resource) electrically connects at any instant only to one socket (and one device therein) in performing each separate test. After testing of one socket (and one device therein), the chuck, as applicable in the configuration, either posits the next device for testing in another respective socket for this next device and tests via that respective socket because of the parallel electrical connectivity of that socket; or removes the tested device from the one socket and places the next device in that same socket for the test via that same socket of the next device.
Furthermore, in certain other configurations, a single interface board can have more than one test socket and the sockets are not connected in parallel (i.e., not parallel for purposes of concurrent use of same tester resource), but the tester 104 has a separate respective distinct tester resource connected to each socket, respectively. Such multiple sockets on the interface board are each connected only to the respective distinct (different) tester resource from the single tester 104. In effect, the tester 104 can perform different tests on each socket, but not the same tests on each socket concurrently. In such configurations, the chuck of the manipulator arm 109 can similarly pick-up, position and locate in the sockets more than one device in each pass of the manipulator arm 109 (e.g., two devices in the pass of the arm 109). Nonetheless, the different tests are performed as to the respective distinct sockets, not the same test at once. For purposes herein, the singular term “socket” is intended and to be understood as including this type of configuration (of more than one socket), as well.
There can be certain other special cases of configurations, where the tester resources can drive signals from the tester to multiple devices (in multiple respective sockets) at the same time. Such resources include power supplies, digital drivers, and analog waveform generators. In each special case, however, the resource is considered an output resource from the particular tester, and the tester in such use must be specially configured and have functionality required to perform the separate distinct testing in concurrent manner. Most conventional testers do not have such special configuration or functionality and, in any event, any such special testers can be significantly more expensive and/or limited in application when compared to most conventional testers. For purposes herein, the singular term “socket” also means and includes the multiple socket arrangement for this type of special case of tester with such capabilities.
As is typical, the robotic handler 108 in each of the foregoing configurations mechanically moves and operates to pick up and handle the device 102 (i.e., which, as just discussed, can actually be more than one device depending on chuck, arm, and handler design and capabilities), from among one or more devices to be tested. Once the device 102 to be tested is picked-up by the manipulator arm 109 of the handler 108, the handler 108 controls the manipulator arm 109 to transfer the device 102 into position in the appropriate socket 110 of the interface board 106 (i.e., which socket, socket, can similarly actually be more than one socket either in parallel or as with the special case tester, depending on design and capabilities as have just been discussed). The tester 104 then commences to test the device 102. After the test is completed by the tester 104, the handler 108, via the control of the manipulator arm 109 and its operation, mechanically removes the device 102 from the socket 110 and transfers the device 102 to a location of tested devices.
In operations of the conventional system 100, a set of devices to be tested are staged at the input to the handler 108 by a human operator. The operator then instructs the handler 108 to begin retrieving devices to be tested and to stage the next available device by inserting it into the test socket 110. Once the handler 108 has sensed that the first device 102 is in place in the test socket 110 and ready for test, the handler 108 issues a start-of-test signal to the tester 104. In response to the start-of-test signal, the tester 104 executes a test program that electrically stimulates, via the test socket 110, the device 102 under test and measures the output response from the device 102. The tester 104 compares the output response to a set of expected response data and judges the results as either a “pass” or a “fail” of the device 102.
If the interface board contains multiple test sockets and the tester is capable of concurrent testing with different tester resources of the tester, as with the certain specialized tester previously mentioned, the tester must query the handler status to determine which test sockets have devices ready for test and which do not. The tester can then ignore failing test results from empty test sockets and test only active test socket sites with devices inserted. Of course, as previously mentioned, such special testers with these capabilities are relatively uncommon, expensive, and limited in application.
Once the test program has concluded testing for the device 102 and a pass/fail determination of the test results has been made by the tester 104, the tester 104 communicates back to the handler 108 the test result data for the device 102 just tested and follows by an end-of-test signal to the handler 108. The handler 108 receives the end-of-test signal from the tester 104, and the handler 108 uses the test results data to disposition the device 102 just tested by control and operations of the manipulaotor arm 109 of the handler 108, into an output staging area for tested devices, such as separate holding areas for passing devices and for failing devices, respectively.
If the interface board contains multiple test sockets and the tester is capable of concurrent testing with different tester resources of the tester, as with the certain specialized tester previously mentioned, the tester must communicate results data for each of the active test socket locations that is site specific and the handler must disposition each of the devices accordingly. Again, any such arrangement requires specialized tester and possibly special handler equipment, and these each have the problems of expense and limited applications.
In ongoing operations of the system 100, once the handler 108 has dispositioned the device 102 just tested, the process repeats in succession until there are no additional untested devices remaining to be tested, or until any error condition in the handler status or tester halts operation, or until a human operator intervenes to halt the testing.
In each case of a test in this conventional system 100, the handler 108 individually obtains and transfers the respective device 102 then being tested. During the mechanical operations of the handler 108 (and, in particular, the manipulator arm 109 thereof) in picking up, setting in the socket 110, and locating after test, the tester 104 remains idle without conducting any test. The index time for the system 100 is substantially the time required for the mechanical operations of the handler 108 when removing and dispositioning the tested device and then retrieving and inserting each next successive untested device for testing. The index time also includes any time interval between the end-of-test signal from the tester 104 to the handler 108 and the next start-of-test signal from the handler 108 to the tester 104.
Referring to FIG. 4, a conventional process 400 for testing a device includes a step 402 of initiating a first manipulator. In the step 402, for example, a signal is communicated to a robotic handler having the first manipulator. The signal is communicated by a tester or other source, to indicate to the handler that the first manipulator should initiate actions to obtain and locate a device for testing. The device is, for example, a semiconductor device or any other manufactured part or element that is to be tested by the particular tester.
In a step 404, the first manipulator mechanically moves its arm to retrieve a first device for testing. The first manipulator grips or otherwise retains the first device. Then, in a step 406, the first manipulator mechanically picks-up and manipulates the first device, for example, appropriately orienting the first device for testing. In a step 408, the first manipulator mechanically moves the first device to an interface board connected to the tester and inserts the first device in a socket or other test cell of the interface board.
Once the first device is located in the socket or other test cell, the tester commences a step 412 of testing of the device. Testing can include power test, logic test, and any of a wide variety of other quality control or device conformance tests. The testing may take some period of time for completion, depending on the test being performed. During the testing, the first manipulator maintains the first device in position at the interface board for the test.
When the testing step 412 is completed, the tester signals to the handler and the first manipulator is activated to mechanically remove the device, in a step 414, from the socket or other test cell. The first manipulator then moves the first device to a desired post-test location in a step 416. In a step 418, the first device is released by the first manipulator at the post-test location.
The process 400 then returns to the step 402, in order to repeat the steps with respect to a next test device and a next test of the device. As previously mentioned, the time during the process 400 required for the operations of the first manipulator of the handler to pick-up, move, place, remove and dispense of each device, is referred to as the “index time” for the test system. During the index time of operations of the first manipulator, the tester remains in an idle state in which no test is being conducted. The index time that is required in such process 400 delays and limits the entire process 400.
Referring to FIG. 13, conventional testers include pin electronics cards 1302 that provide for the various tests performable by the tester, both analog and/or digital. Each pin electronics card 1302 contains one or more test resources, represented by the blocks 1302a-c. The test resources of each pin electronics card 1302 can include different, more, less or other elements from those of blocks 1302a-c, which are solely for example purposes, including, without limitation, such as the following:                1. a driver that drives a voltage to an input pin (or pad) on the device under test (“DUT”);        2. a receiver or comparator that measures the voltage on an output pin (or pad) of the DUT;        3. a current load of a 50 Ohm resistive connection to a variable termination voltage and current clamps which change the 50 Ohm resistance to whatever is required to hold the current load at a fixed and programmable value;        4. memory that stores data states (drive and receive), timing, and voltage thresholds;        5. a controller that sequences the drive and receive data to and from the DUT at a programmed rate;        6. fail memory that stores information on when the expected data does not match the actual data measured by the operation of the pin electronics of the card, individually and in synchronization the receivers;        7. software that manages with other tester resources; and        8. a calibration system that measures the length of the communication connection from the pin electronics to the DUT resources on the corresponding pin on the DUT.The pin electronics of the card 1302 can also include test hardware of an analog nature, such as analog to digital converters, digital to analog converters, and time measurement systems. The particular types of test resources of the card 1302 enable testing of the device under test (“DUT”) by the tester.        
Each pin electronics card 1302 includes test resources for one or more tester channels 1304, each tester channel 1304 serving to test, typically, at a single pin of the DUT. As previously mentioned, there are certain special configurations or functionalities where tester resources could drive signals from the tester to multiple pins at the same time; but most conventional testers do not have this capability and, in any event, the capability is significantly more expensive and quite limited in application. So, for purposes of discussion and understanding, the typical circumstance of test resources that drive a single pin of a single device, via a tester channel connected to the single pin of the device, is described herein. (It should be understood, however, that even if a “special capability” situation is presented, the presently disclosed embodiments will provide advantages as those skilled in the art will know and appreciate.) Referring to FIG. 14, in conjunction with FIG. 13, another functional representation of the foregoing shows various pin electronics cards 1402, each including various respective test resources 1402a-d, with the separate respective tester channel 1404 connecting the applicable test resources 1402a-d to a single pin of a DUT (not shown in detail).
Referring to FIG. 15, conventional testers have pin electronics cards that include relays, such as the AC Relay of the exemplary pin electronics card 1500. The AC Relay, for example, electrically disconnects the test resources of the pin electronics card provided over the tester channel 1504, from a single pin of a DUT (not shown in detail) to which the tester channel 1504 is connected.
Referring to FIG. 18, a conventional test system 1800 (presented in somewhat more detail as an example configuration) includes a handler 1802 of a test cell 1803, and an automated test equipment (“tester”, also known as “ATE”) 1806. The handler 1802 of the system 1800 includes various mechanical (typically physically moving) conveyors/transports and robotic manipulation arms, and respective elements, for positioning and dispositioning respective DUTs in testing successive DUTs. For example, DUTs are positioned for testing at input trays 1820 capable of holding pluralities of to-be-tested DUTs. An input manipulator 1822 of the system 1800 moves successive ones of the to-be-tested DUT (or successive pairs or other number of DUTs) from the input trays 1820 to an input stage 1810 of the system 1800. The DUT is positioned at the input stage 1810 for transport to and through the test cell 1802 in testing of the DUT. The test cell 1802 can include various processing units, such as temp soak and hold stages 1812 (and the like or other pre-test and/or post-test units/prepping).
The test cell 1802 is equipped with a core 1814. The core 1814 includes, among other electrical interfacing and connecting elements, an electrically stimulatable socket 1808. The socket 1808 has pin connectors to respective test resources of the tester 1806. Respective pins/connectors of the socket 1808 correspond to the electrical input/output pins for the DUT located in appropriate position in the socket 1808 for testing. (As previously mentioned, possibly more than one socket and DUT therein are concurrently testable via a particular test resource(s) in certain configurations of handler and tester, if applicable; however, such configurations and systems are not generally practical or feasible and have not been widely employed as a result of limitations, problems, impediments and the like). The to-be-tested DUT is, thus, positionable (as hereinafter further detailed) in the socket 1808 for testing by the tester 1806. The tester 1806 of the system 1806 performs testing on a posited DUT of the socket 1808, via a particular respective tester resource of the tester 1806 at each corresponding pin of the DUT so positioned in the socket 1808. Tests conducted by the tester 1806, via each respective test resource, accord to the test protocols and capabilities of the tester 1806 for the particular test then conductable via the system 1800.
As previously mentioned, the handler 1802 includes a core manipulator 1804 (i.e., “manipulator arm”). The core manipulator 1804 of the handler 1802 positions each next to-be-tested DUT in the socket 1808 for testing of the DUT by the tester 1806. The core manipulator 1804 must robotically, mechanically operate as to each next to-be-tested DUT by obtaining the DUT, for example, the core manipulator 1804 retrieves the DUT at the temp soak and hold stage 1812, and then positions the DUT for testing, such as into an empty socket 1808 of the core 1814. Once the handler 1802, via operations of the core manipulator 1804 in retrieving/positioning the DUT, senses that the DUT is in place in the socket 1808 and ready for test, the handler 1802 triggers a start-of-test by signaling to the tester 1806. In response, the tester 1806 executes a test program according to the test protocol for the test then-being conducted. In the test, the tester 1806 electrically stimulates, via the socket 1808 at each pin and respective test resource for the pin, the DUT in the socket 1808 and measures output response. Upon completion of the test by the tester 1806 for the DUT then in the socket 1808, the tester 1806 communicates end-of-test result to the handler 1802. The core manipulator 1804 is controlled by the handler 1802 to then disposition the DUT from the socket 1808 and locate the DUT in an applicable disposition stage 1816 of the handler 1802 (with such dispositioning operation of the core manipulator 1804, and the particular applicable disposition stage 1816, corresponding to a pass/fail result of the test and as has then been indicated to the handler 1802 for the particular DUT).
The DUT which has then been tested by the tester 1806 and so dispositioned from the socket 1808, progresses by transport mechanism of the handler 1802, for example, to an output stage 1818. An output manipulator 1824 further progresses the then-tested DUT from the output stage 1818, to a corresponding bin tray 1826 for the DUT. For example, the tested DUT is positioned as output of the handler 1802, and the system 1800, in accordance location in accordance with the test result obtained for the DUT.
Thereafter, to continue testing of a next to-be-tested DUT (from among remaining ones of the DUTs staged as input for testing), the core manipulator 1804 obtains any next successive to-be-tested DUT that is then located (via operations of the input manipulator and transport of the handler 1802) at the temp soak and hold stage 1812 (or otherwise if and as applicable, per the system 1800 test operation). This next DUT is positioned by the core manipulator 1804 in the socket 1808 of the core 1814, and test by the tester 1806 next performed via the socket 1808 on that then-posited DUT at the socket 1808. Upon test completion of this DUT, the core manipulator 1804 next dispositions that then-tested DUT from the socket 1808 and moves this DUT to the disposition stage 1816 for further progression of post-test handling via the handler 1802. The handler 1802 input progression of respective to-be-tested DUTs, positioning/disposition by the core manipulator 1804 of each successive DUT in the socket, and output progression of the DUT on test completion, continues until all DUTs are tested (or until a shutdown, error or other interruption occurs).
In effect, upon test commencement during successive testing of DUTs via the test cell 1802, the tester 1806 acts as a slave and the handler 1802 acts as a master in controlling a testing process. That is, the handler 1802, via the core manipulator 1804, mechanically moves each successive DUT to position it in the socket 1808 for testing and dispositions it from the socket 1808 after testing on it is completed. When the DUT is posited in the socket 1808, the handler 1802 signals the tester 1806 to commence the applicable test (i.e., via the tester resources on resource channels to the socket 1808 and therein posited DUT). As is conventional, the handler 1802, via the core manipulator 1804 and other functional elements of the handler 1802 and system 1800 as may be applicable (e.g., input stage 1810, temp soak and hold 1812, core 1814, disposition 1816, output stage 1818, and associated transports), moves/transports each DUT through applicable stages/procedures required to position, test, and disposition, according to the relevant process protocols and steps and generally as herein so described.
The tester 1806, as previously discussed, connects a single test resource to the pin of the socket 1808 at any instant of testing. For example, whenever the DUT is located in the socket 1808, the tester 1806 conducts testing via the single test resource at the pin, and thereby electrically on the DUT through connection to the pin in the socket 1808. Each respective to-be-tested DUT must, therefore, be successively located in the socket 1808, electrically connecting applicable pin(s), for testing by the tester 1806 (and each test resource thereof that is applicable and corresponding to the respective applicable pin(s)). In so locating each next respective to-be-tested DUT in the socket 1808, and then dispositioning each one from the socket 1808 upon tester 1806 test completion, the core manipulator 1804 operates through a series of steps/movements, and repeats these over and over, until all DUTs are tested. Particularly, the core manipulator 1804 as to each next to-be-tested DUT must robotically proceed to retrieve the next to-be-tested DUT (such as at the temp soak and hold stage 1812), position the DUT at the socket 1808, and posit the DUT in the socket 1808. Once testing of the DUT in the socket 1808 by the tester 1806 (and its respective test resource at each pin) is completed, the handler 1802, via the core manipulator 1804, must further proceed to robotically remove the DUT from the socket 1808 and robotically reposition it elsewhere (such as the disposition stage 1816) for the next successive operations of testing on next DUT in the process of the system 1800. Of course, prior to performing any active test by the tester 1806 as to each next to-be-tested DUT, the core manipulator 1804 (and handler 1802 as a whole) must have previously dispositioned any DUT remaining in the socket 1808, such as from the immediately prior test operation. Only thereafter can the handler 1802, via the manipulator arm 1804, then continue the testing operations by robotically proceeding to obtain and then position the next to-be-tested DUT in the socket 1808, and so forth, on and on until all DUTs are tested or the operations are otherwise halted.
Of course, once each next one of to-be-tested DUT has been positioned in the socket 1808, a next testing is then performed on that next DUT by the tester 1806 and each test resource thereof corresponding to the respective pin. Time lapse occurs between active testing by the tester 1806 on successive DUTs, during the time required for the core manipulator 1804 to obtain and position a next to-be-tested DUT in the socket 1808, and then to disposition the tested DUT from the socket 1808, and on as to each next successive to-be-tested DUT with repetition of these time lapse periods of active testing. Further, during active testing by the tester 1806 on any DUT then posited in the socket 1808 at any instant—i.e., when the DUT is located in the socket 1808 and a respective test resource electrically stimulates its corresponding pin (upon posit/active test/before disposit)—the core manipulator 1804 remains occupied in handling the DUT then-being tested by the tester 1806. The core manipulator 1804, therefore, remains occupied in operating with the then-being tested DUT, and time is required for dispositioning, next positioning, next test, next dispositioning and onward repetition. In effect, in the conventional system 1800 operations, either the tester 1806 is substantially idle and not actively testing at instants that the core manipulator 1804 is active, or when the tester 1806 is actively testing, the core manipulator 1804 is occupied handling the DUT then under test or with of that DUT through testing positioning/test/disposition rather than any progression of next DUT for testing.
Time periods of idle active testing and occupied/in-use core manipulator 1804, therefore, aggregate to significant index time losses in testing operations of the system 1800. The periods of inactivity of testing by the tester and of the occupied/in-use core manipulator/handler elements during positioning/test/dispositioning, are experienced as to each DUT and each successive DUT. When multiple DUTs are tested, as is the usual application (in fact, large numbers of DUTs are typically tested in continuing operations), each component of index time causes non-optimal equipment utilization and longer times to test operations completion for the multiple DUTs. Thus, the conventional system 1800, and its elements and operations of the handler 1802 (and core manipulator 1804 thereof) of the system 1800, coupled with the interruption of active test conduct by the tester 1806 during those core manipulator operations with successive DUTs, has adverse implication to test operations time, equipment use optimization, and entire test process.
As has been disclosed in the related and/or incorporated applications to the present application and as further disclosed herein, the conventional designs of testers (ATEs) and pin electronics cards and also of handlers and handler operations results in undesired index time occurring in the testing process. This application and the related/incorporated applications disclose certain problems primarily resulting in undesired index time because each tester channel of the tester 1806 can connect a respective tester resource to only the single pin of a DUT then being tested at any instant (and the consequence thereof that handler operations must therefore interrupt between active testing of successive DUTs by the tester for periods required for progression from disposit of DUT to posit of each next respective DUT in the handler and tester master/slave operations).
Additionally, as further disclosed in this application, in conjunction with and as also pointed out in the related/incorporated applications, certain problems primarily resulting in undesired index time because of occupied/in-use handler elements/features, including manipulator arms of the handler and also other aspects of the handler such as each single path for processing (i.e., single input stage, single temp soak and hold stage, single disposition and output stage, as well as single transport mechanisms into, through and from test cell and the like) are addressed in order optimize and improve testing systems and test operations and processes, including those of the handler elements and others.
Furthermore, certain other problems of conventional testing systems and processes primarily resulting in downtime because of mechanical and other malfunction and maintenance of the handler, and stages, processes, and elements of the handler (including, but not limited to, manipulator arm and other stages) are addressed by the present disclosure.
From the foregoing description of the conventional system and method for testing devices, it can be readily appreciated and understood that reductions of index time required in the conventional system and method would provide significant advantages. Moreover, it can be appreciated and understood that any reductions that require any previously known specialized tester and handler equipment can be inordinately expensive and limited in application.
Further from the foregoing, it can be readily appreciated and understood that delays and idle test equipment, such as because of handler malfunction, maintenance, or other similar reason, are problematic. Significant advantages would be achieved by reducing the occurrence and possibility for these problems.
The present invention provides these and other advantages and improvements, including improvements and nuances in the foregoing respects, without problems and disadvantages previously incurred in conventional practice, systems, and operations.